3 Credit Hour Course
Intended For Level 0 Term 0 Students
Prerequisite:
VLSI design cycle, physical design cycle, design styles; Basic graph algorithms and computational geometry algorithms related to VLSI layout; Partitioning algorithms: group migration algorithms, simulated annealing and evaluation, performance driven partitioning; Floor planning and placement algorithms: constraint based floor planning, rectangular dualization and rectangular drawings, integer programming based floor planning, simulation based placement algorithms, partitioning based placement algorithms; Pin assignment algorithms; Routing algorithms: maze routing algorithms, line prob algorithms, shortest-path based and steiner tree based algorithms, river routing algorithms, orthogonal drawing based algorithms; Compaction algorithms: constraint-graph based compaction, virtual grid based compaction, hierarchical compaction; Algorithms for Multi-Chip Module (MCM) physical design automation.
